Key Takeaways
- $225M raised in an oversubscribed Series A round led by Maverick Silicon, closing March 23, 2026, valuing Kandou AI at $400 million
- Strategic heavyweights on board: SoftBank Group, Synopsys, Cadence Design Systems, and Alchip Technologies all participated, signaling deep conviction from the AI supply chain
- The mission: Kandou AI’s copper-based signaling technology targets interconnect and memory bandwidth bottlenecks that now limit AI cluster performance more than raw compute power
- Capital deployment plan: Funds go toward manufacturing scale-up, expansion of hyperscale customer partnerships, and pushing the next-gen chip and IP portfolio past the 448G bandwidth barrier
Quick Recap
Lausanne, Switzerland-based Kandou AI formally closed a $225 million strategic funding round on March 23, 2026, according to an official press release and confirmed by Bloomberg.
The oversubscribed Series A was led by new investor Maverick Silicon, with strategic participation from SoftBank Group Corp., Synopsys, Cadence Design Systems, and Alchip Technologies Limited, alongside several existing investors. The round values the AI connectivity silicon company at $400 million, per CEO Srujan Linga.
Kandou AI’s Tech Explained: Faster Data, Lower Power
Kandou AI, originally spun out of EPFL (Swiss Federal Institute of Technology Lausanne) in 2011 under founder Amin Shokrollahi, has spent over a decade building a portfolio of more than 300 patents around a fundamental insight: copper wire, when signaled correctly using information theory, can dramatically outperform conventional chip interconnects.
The company’s flagship technology, CNRZ-5 Chord signaling, uses six wires to transmit data simultaneously where standard differential signaling uses two. The result is the ability to move up to five bits at once at half the power of competing approaches, and over longer physical distances, giving chip architects more flexibility in how they lay out multi-die processors.
Its Glasswing product family applies this to die-to-die links inside advanced processor packages, removing the need for an interposer and shrinking the main chiplet footprint in multi-die designs. Kandou AI claims Glasswing can move data between chiplets faster and at lower energy than alternatives, which is increasingly critical as modern AI accelerators are composed of stacked memory and compute dies.
The new capital will fund three specific priorities: manufacturing ramp-up of its high-performance AI connectivity chips, deepening partnerships with hyperscale and AI infrastructure customers globally, and advancing a chip and IP roadmap aimed at multi-terabit connectivity piercing the 448G barrier. CEO Srujan Linga, a former Goldman Sachs managing director who joined the company last year and led the pivot toward AI infrastructure, stated: “Our initial products will focus on AI systems and high-speed rack connectivity piercing the 448G barrier and beyond, with plans to expand into broader AI infrastructure over time.”
AI’s Connectivity Crisis
The broader context here is not subtle. As AI model sizes have scaled exponentially, the compute side of the equation has gotten enormous attention. But the interconnect layer, the physical plumbing that moves data between GPUs, between chips, and between processors and memory, has quietly become the harder problem.
Kandou AI’s own press release frames this directly: “The performance of AI clusters is increasingly not constrained by compute, but by the speed and efficiency of data interconnects connecting compute infrastructure with memory. Traditional networking and interconnect technologies, designed for a pre-AI world, cannot keep pace.”
The investor roster makes this strategic urgency visible. Synopsys and Cadence Design Systems are the two dominant providers of chip design software globally. Their direct investment is not passive capital; it signals that they see Kandou AI’s IP as likely to be integrated into the silicon design workflows that their customers use to build next-generation AI chips. SoftBank’s involvement through its Vision Fund orbit confirms a macro-level bet on AI infrastructure components, consistent with its broader portfolio thesis.
From a market timing standpoint, the AI infrastructure capital cycle is at full tilt. Ayar Labs, which develops optical interconnects as a competing approach to the same data movement problem, raised $500 million in early March 2026 at a $3.75 billion valuation. Eliyan Corporation, a Santa Clara-based chiplet interconnect specialist, closed a $50 million round in January 2026 backed by AMD, Arm, Meta, and Intel Capital.
Competitive Landscape
Key Players in AI Interconnect and Silicon Signaling
| Feature / Metric | Kandou AI | Eliyan Corporation | Ayar Labs |
| Technology Approach | Copper-based Chord signaling (CNRZ-5); SerDes and retimer ICs | Chiplet interconnect PHY (NuLink) and scale-up NuGear chiplets | Silicon photonics; in-package optical I/O (TeraPHY) |
| Latest Funding | $225M Series A (March 2026) | $50M strategic round (January 2026) | $500M Series E (March 2026) |
| Valuation | $400M | Not disclosed | $3.75 billion |
| Key Investors | Maverick Silicon, SoftBank, Synopsys, Cadence, Alchip | AMD, Arm, Meta, Intel Capital, Samsung Catalyst | Neuberger Berman, AMD, ARK Invest, Qatar Investment Authority |
| Target Bandwidth | 448G and beyond; multi-terabit roadmap | 1.6T to 12.8Tbps (NuGear scale-up); 224G and 448G C2C | Terabit-scale optical I/O for AI training/inference |
| Core Use Case | AI cluster rack connectivity; die-to-die links in multi-chip AI processors | Die-to-die links; HBM memory expansion; scale-up AI networks | Replacing electrical I/O with optical for AI GPU interconnects |
| Total Funding to Date | ~$500M+ (cumulative across rounds) | ~$50M+ (earlier funding undisclosed) | $870M total |
| Heritage | EPFL spin-off (2011); 300+ patents in signaling IP | Founded by semiconductor veterans; die-to-die interconnect specialist | Founded 2015; silicon photonics from MIT research |
Strategic Read
Kandou AI and Eliyan compete most directly in copper-based, electrical interconnect solutions for AI chiplet architectures, with Eliyan holding a cleaner chiplet-native story and an elite hyperscaler investor base (AMD, Meta, Arm), while Kandou AI brings a deeper IP moat built on over a decade of Chord signaling patents and now carries the credibility of EDA giants Synopsys and Cadence as strategic co-investors.
Ayar Labs operates at a higher valuation in a different lane entirely: optical interconnects command more investor excitement right now due to bandwidth ceiling arguments, but optical solutions carry higher manufacturing complexity and cost, which is exactly the gap Kandou AI’s copper-first approach is designed to exploit at scale.
TechnoTrenz’s Takeaway
I want to be direct here: I think this round is a genuinely big deal, and not just because of the headline number.
What stands out to me is the quality of the strategic investors, not the quantity. When Synopsys and Cadence, the two companies whose tools are used to design virtually every advanced AI chip on the planet, write checks into a connectivity IP startup, that is not a passive financial bet. In my experience covering semiconductor funding, that kind of involvement typically signals that the acquirers-in-waiting or integration partners are already in early conversations. The EDA layer and the silicon IP layer are about to get much closer together, and Kandou AI just put itself at that intersection.
I am also watching the copper vs. optical debate play out in real time, and I think the market is going to be big enough for both to win. Ayar Labs at $3.75B is the optical bull case. Kandou AI at $400M is the copper efficiency bull case. For hyperscalers who need to deploy at massive scale right now, copper is cheaper and easier to manufacture. That is a real commercial advantage, not a consolation prize.
